MODIFIED VEDIC MULTIPLIER, WHICH UTILIZES THE MODIFIED HSCG-SCG ADDER TO ACHIEVE HIGH-SPEED MULTIPLICATION

Abstract

Modified Vedic Multiplier is an approach to multiplication that integrates the ideas of ancient Vedic Mathematics. The technique employs a sequence of vertical and horizontal computations to carry out multiplication. The Modified Half Sum Carry Generation (HSCG) - Full Sum Carry Generation (SCG) Adder is an enhanced iteration of a traditional binary adder. The system employs a decoder to produce partial products and a carry tree to obtain the final result. The Modified Vedic Multiplier, which incorporates the Modified HSCG-SCG Adder, has several benefits compared to traditional multipliers. The advantages include reduced latency, lower energy use, and improved speed. It is particularly well-suited for usage in applications that necessitate rapid multiplication, such as digital signal processing, image processing, and cryptography. The technique can be executed via Verilog HDL, a specialized language specifically tailored for describing hardware. The concept can be replicated and confirmed using a hardware emulation tool such as Vivado. Keywords: Vedic Multiplier, HSCG-SCG, Multiplier, Adder, Xilinx, Verilog.